1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, particularly, to a method of manufacturing a semiconductor device having multiple gate oxide films.
2. Description of a Related Art
In an IC, such as a PDP (plasma display panel) driver and an LCD (liquid crystal display) driver, a semiconductor in which transistors having different threshold voltages are mounted in a mixed manner on the same substrate may sometimes be used. Such a semiconductor device is provided with, for example, two transistors, i.e., a transistor having a relatively low threshold voltage (hereinafter referred to as “a low-voltage transistor)” and a transistor having a relatively high threshold voltage (hereinafter referred to as “a high-voltage transistor.)” In manufacturing such a semiconductor device, it is necessary to form a thin gate oxide film for a low-voltage transistor and a thick gate oxide film for a high-voltage transistor. Such multiple gate oxide films having different film thicknesses are hereinafter referred to as “multiple gate oxide films.” A semiconductor device having multiple gate oxide films is hereinafter referred to “a multigate semiconductor device.”
FIG. 1A to FIG. 1I are each a sectional view that shows a conventional process for manufacturing a multigate semiconductor device. In FIG. 1A to FIG. 1I, an element region in which a low-voltage transistor is formed is denoted by the reference character “L” and an element region in which a high-voltage transistor is formed is denoted by the reference character “H.”
First, a field oxide film 31 is formed on a semiconductor substrate 30 by a selected oxidation process (LOCOS: local oxidation of silicon), whereby element isolation is performed. Subsequently, a dummy oxide film 32 is formed on the whole surface, and a nitride film 33 is formed on this dummy oxide film 32. As a result of this, the structure shown in FIG. 1A is obtained.
Next, by performing the patterning of a photoresist, a pattern 34 having an opening in a region in which a gate electrode of a high-voltage transistor (an electrode formation region) is formed on the nitride film 33. Subsequently, by performing dry etching in which this pattern 34 is used as a mask, the nitride film 33 and the dummy oxide film 32 in the above-described electrode formation region are removed. As a result of this, the structure shown in FIG. 1B is obtained.
Next, the pattern 34 is removed. Subsequently, by a selective oxidation method in which the nitride film 33 is used as a mask, a gate oxide film 35 of a high-voltage transistor is formed in the above-described electrode formation region. In this step of selective oxidation, a thin oxide film 36 is formed on the nitride film 33. As a result of this, the structure shown in FIG. 1C is obtained.
Next, the oxide film 36 and the nitride film 33 are removed by performing wet etching. On that occasion, also the surface of the gate oxide film 35 of a high-voltage transistor is subjected to wet etching treatment. Furthermore, the dummy oxide film 32 is removed by performing wet etching, and the surface of the semiconductor substrate 30 in the element region L of a low-voltage transistor is exposed. Also on that occasion, the surface of the gate oxide film 35 of a high-voltage transistor is subjected to wet etching treatment. As a result of this, the structure shown in FIG. 1D is obtained.
Next, as shown in FIG. 1E, a gate oxide film 37 for a low-voltage transistor is formed on the semiconductor substrate 30.
Next, polycrystalline silicon 38 is formed on the whole surface. Subsequently, by performing the patterning of a photoresist, a pattern 39 and a pattern 40 are formed respectively on the electrode formation region of a low-voltage transistor and the electrode formation region of a high-voltage transistor. As a result of this, the structure shown in FIG. 1F is obtained.
Next, by performing dry etching in which these patterns 39, 40 are used as masks, the above-described polycrystalline silicon 38 is selectively removed. After that, the patterns 39, 40 are removed. As a result of this, as shown in FIG. 1G, a gate electrode 41 of a low-voltage transistor and a gate electrode 42 of a high-voltage transistor are formed.
Next, as shown in FIG. 1H, by performing impurity ion implantation in which the above-described gate electrodes 41, 42 are used as masks, an LDD (lightly doped drain) is formed in the semiconductor substrate 30. Subsequently, impurity ions are implanted in source-drain regions of the low-voltage transistor and high-voltage transistor. Source-drains of the low-voltage transistor and high-voltage transistor are formed by causing the impurities to diffuse thermally.
Next, the gate oxide film 37 is removed by using the above-described electrodes 41, 42 as masks. In this way, as shown in FIG. 1I, a multigate semiconductor device in which a low-voltage MOS transistor and a high-voltage MOS transistor are mounted in a mixed manner on the same substrate is completed.
According to the above-described manufacturing method, the surface of the gate oxide film 35 of a high-voltage transistor is subjected to wet etching treatment while the semiconductor device is being worked from the condition shown in FIG. 1C to the condition shown in FIG. 1D. For this reason, the film quality of the gate oxide film 35 deteriorates, posing the problem that the reliability of the gate oxide film 35 of a high-voltage transistor decreases.
The Japanese Patent Laid-Open No. 6-196639 discloses another process for manufacturing a multigate semiconductor device. FIG. 2A to FIG. 2H are each a sectional view that shows the manufacturing process disclosed in the Japanese Patent Laid-Open No. 6-196639. In FIG. 2A to FIG. 2H, an element region in which a low-voltage transistor is formed is denoted by the reference character “L” and an element region in which a high-voltage transistor is formed is denoted by the reference character “H.”
First, a field oxide film 51 is formed on a semiconductor substrate 50 by a selected oxidation process, whereby element isolation is performed. Subsequently, a dummy oxide film 52 is formed on the whole surface. After that, by performing the patterning of a photoresist, a pattern 53 having an opening in a source-drain region of a high-voltage transistor is formed. As a result of this, the structure shown in FIG. 2A is obtained. And by performing impurity ion implantation in which this pattern 53 is used as a mask, an LDD is formed in the semiconductor substrate 50. After the removal of the pattern 53, a pattern (not shown) having an opening in a channel region of a high-voltage transistor is formed. And by using this pattern as a mask, channel ions are implanted in the semiconductor substrate 50 through the dummy oxide film 52. After that, the pattern is removed.
Next, a nitride film 54 is formed on the whole surface. Subsequently, by performing the patterning of a photoresist, a pattern 55 having an opening in an electrode formation region of a high-voltage transistor is formed on the nitride film 54. Furthermore, by performing dry etching in which this pattern 55 is used as a mask, the nitride film 54 and the dummy oxide film 52 in the electrode formation region are removed. As a result of this, the structure shown in FIG. 2B is obtained.
Next, after the removal of the pattern 55, by a selective oxidation process in which the nitride film 54 is used as a mask, a gate oxide film 56 of a high-voltage transistor is formed in the above-described electrode formation region. In this step of selective oxidation, a thin oxide film 57 is formed on the nitride film 54. Subsequently, polycrystalline silicon 58 is formed on the whole surface. And by performing the patterning of a photoresist, a pattern 59 is formed in the electrode formation region of a high-voltage transistor. As a result of this, the structure shown in FIG. 2C is obtained.
Next, by performing dry etching in which this pattern 59 is used as a mask, the above-described polycrystalline silicon 58 is selectively removed. After that, the pattern 59 is removed. As a result of this, as shown in FIG. 2D, a gate electrode 60 of a high-voltage transistor is formed.
Next, the oxide film 57 is removed by performing wet etching, and furthermore the nitride film 54 is removed by performing dry etching. Subsequently, a pattern 61 which covers an element region H of a high-voltage transistor is formed. As a result of this, the structure shown in FIG. 2E is obtained. And using the pattern 61 as a mask, channel ions are implanted through the dummy oxide film 52 into the semiconductor substrate 50 in an element region L.
Next, the pattern 61 is removed and the dummy oxide film 52 is removed by performing wet etching. As a result of this, the structure shown in FIG. 2F is obtained.
Next, a gate oxide film 62 for a low-voltage transistor is formed on the whole surface. Subsequently, polycrystalline silicon 63 is formed on the gate oxide film 62. Furthermore, by performing the patterning of a photoresist, a pattern 64 is formed in an electrode formation region of a low-voltage transistor. As a result of this, the structure shown in FIG. 2G is obtained.
Next, by performing dry etching in which the pattern 64 is used as a mask, the above-described polycrystalline silicon 63 is selectively removed. As a result of this, as shown in FIG. 2H, a gate electrode 65 of a low-voltage transistor is formed.
Next, the above-described LDD portion of a high-voltage transistor is covered with a prescribed pattern (not shown), and impurity ions are implanted in source-drain regions of the low-voltage transistor and high-voltage transistor. Sources-drains of the low-voltage transistor and high-voltage transistor are formed by causing the impurities to diffuse thermally. And the gate oxide film 62 is removed by using the above-described electrodes 65, 60 as masks. In this way, a multigate semiconductor device in which a low-voltage MOS transistor and a high-voltage MOS transistor are mounted in a mixed manner on the same substrate is completed.
According to the manufacturing method disclosed in the Japanese Patent Laid-Open No. 6-196639, after the formation of the gate oxide film 56 of a high-voltage transistor, the polycrystalline silicon 58, is subsequently formed (see FIG. 2C). In the succeeding steps, the exposure of the surface of the gate oxide film 56 of a high-voltage transistor does not occur, and it might be thought that the film quality of the gate oxide film 56 does not deteriorate due to etching.
Also, according to the manufacturing method disclosed in the Japanese Patent Laid-Open No. 6-196639, in order to form the gate electrode 65 of a low-voltage transistor, the polycrystalline silicon 63 is selectively removed by performing dry etching in which the pattern 64 is used as a mask (see FIGS. 2G and 2H). On that occasion, the polycrystalline silicon 63 which covers the gate electrode 60 of a high-voltage transistor is also removed. However, it might be thought that the structure after this removal step is in actuality the structure shown in FIG. 3, and not the structure shown in FIG. 2H. That is, the polycrystalline silicon 63 on the side surface of, the gate electrode 60 of a high-voltage transistor is not completely removed, and that as shown in FIG. 3, the polycrystalline silicon 63 which has not been removed remains as residual polycrystalline silicon on the side surface of the gate electrode 60. When this residue polycrystalline silicon 66 exfoliates, it becomes scrap, causing the worsening of yield.